Thanks for clarifying how your code works. I really like your use of the DMA to perform the requested data read with no CPU intervention.
FLASH reads are significantly slower than those from SRAM. SRAM reads typically take 1 clock cycle unless you happen to get bus contention. FLASH reads can be 40x slower if you get a miss in the XIP cache. This post to another thread on this forum covers this issue (along with other memory related ones) quite well:
viewtopic.php?t=344055#p2064092
FLASH reads are significantly slower than those from SRAM. SRAM reads typically take 1 clock cycle unless you happen to get bus contention. FLASH reads can be 40x slower if you get a miss in the XIP cache. This post to another thread on this forum covers this issue (along with other memory related ones) quite well:
viewtopic.php?t=344055#p2064092
Statistics: Posted by adam_green — Mon Dec 25, 2023 10:44 pm