Device Tree • Re: RPI5: Issue with GPCLK0 Clock Generation on GPIO4 in ALT0 Mode

Yes. As long as VCO and divider input maximums are respected.

Thanks a lot for the positive info.

There might be enough plumbing in the clocks framework to just declare parents and clock rates manually in devicetree, and end up with GPCLK sourced from the audio PLL again.

I am not sure I understand. Please does it mean that GPCLKs can be parented by other dividers in the audio tree, e.g. pll_audio_sec or pll_audio_tern (as was before the commit discussed below)?

IIUC originally the GPCLKs allowed to be parented by the audio clks. But the commit https://github.com/raspberrypi/linux/co ... 930b84ac8c removed all the audio clks except for clk_i2s from parents of all RP1_CLK_GPX configs. I understand that commit reasoning to not affect the internal clocks like RP1_CLK_AUDIO_IN, RP1_CLK_PWM0, etc. However, IMO the GPCLKs used as MCLK are exactly for outputing the internal mclk clocks, whatever frequency there is at the moment.

In fact keeping the clk_i2s available just duplicates the pins (clk_i2s is already available from the I2S SCLK pin, IIUC).

The use case for audio does require the GPCLK (= MCLK) output frequency to change - the I2S driver would set the audio_pll_core -> intermediate mclk pll_audio (128 - 1024fs) -> clk_i2s (32/64fs) for the requested samplerate, and the GPCLK parented by pll_audio clk must output the current MCLK. Keeping the GPCLK frequency fixed (when switching between 44.1k and 48k rates) would be of no use for the codec's MCLK signal.

It's a fractional-N PLL with a 10.24bit feedback divider and reference predivider of 1-7. The VCO is rated for 600-2400MHz. Preference is given for the lowest VCO that achieves the target output frequency as that consumes the least amount of power.

Is there any VCO freq recommendation from the generated jitter POV? Something like "the VCO has less jitter at freqs around/below/above xxx MHz".

Thanks a lot. I believe we are heading towards a major improvement of the audio hats when the MCLK signal becomes available. Especially for ADCs which almost always require the MCLK signal and do not feature the internal BCLK -> MCLK PLL.

Statistics: Posted by phofman — Sun Jul 21, 2024 11:49 am

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