The register file on the PIO is 2 general purpose and several reserved registers. Two of the reserved can be used in a general purpose, if you reduce the instruction set. You can implement the FIFO as a register file using DMA, if you know the order of access every time. Use a data structure to weave this into the data stream.
We can implement it in IRQ encoding: (Not SET)Rant:
PIO issues:
Important concepts here are locality and width. We have a means of pipelining more than scalar. The instructions provide some acceleration relative other notions of instructions.
We can implement it in IRQ encoding: (Not SET)
Code:
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 || LOAD | 1 | 1 | 0 | Delay/side-set | 1 | Reg | Address |Reg:00: X01: Y10: ISR11: OSRPIO issues:
- I would have preferred a more performant notion of synchronous input.
- Certain operations/instructions are kind of somersault style thinking or missing.
- Overall the PIO instruction code is a clustered mess.
- I would have preferred each state machine to get their own instruction bank. (Reduces the number of access ports.)
- Have the CPU software manage the issue of CMT.
- Most of the features of a single bank are not really available. (It's a ROM, which has to be managed indirectly.)
- No self modifying code or writes of any kind.
Important concepts here are locality and width. We have a means of pipelining more than scalar. The instructions provide some acceleration relative other notions of instructions.
Statistics: Posted by dthacher — Thu Dec 19, 2024 2:18 pm