DMA is separate from both cores, and it can interleave traffic on different channels.
I doubt it is exhausting the DMA/bus fabric bandwidth with 2 SPIs+I2S, or whatever "_hardware->" means.
I doubt it is exhausting the DMA/bus fabric bandwidth with 2 SPIs+I2S, or whatever "_hardware->" means.
The DMA can perform one read access and one write access, up to 32 bits in size, every clock cycle. There are 16
independent channels, each of which supervises a sequence of bus transfers in one of the following scenarios:
Memory-to-peripheral, Peripheral-to-memory, Memory-to-memory
...
Each channel has its own control and status registers (CSRs) that software can use to program and monitor the
channel’s progress. When multiple channels are active at the same time, the DMA shares bandwidth evenly between the
channels, with round-robin over all channels which are currently requesting data transfers.
The transfer size can be either 32, 16, or 8 bits.
Statistics: Posted by gmx — Wed Apr 30, 2025 5:27 pm