Hello Everyone
We have a case very similar to viewtopic.php?t=347749
We want to use the PIO feature to drive an SPI port - with SCLK x 1,MOSI x 1, MISO x 8, CS_MUX x 3
We have a system already (Pi5/CM5) with 8 SPI devices (STM32G474 x8 - each with very high speed ADC x 4 - each running at 2Mhz - busy with processing @ 100Hz for results)
But due to cable lengths of 1.2 meters to each of the devices (star pattern) standard 74HC244 buffering and IDC cables bandwidth is limited to ~ 5MHz - this is with normal polling of each device - I can broadcast to all devices to sync them for aligned results.
We do not want to use LVDS as it stops being as flexible and would need more refinement. The current design is straight logic with a Custom Pi HAT - 4 layers - good layout slew resistors, termination at each end etc - with individual buffering to each cable. Some latency has been seen in the 74HC151 used (tried other HCT/AC etc as well)
We want to Make a smarter HAT with a RP2350B that can Transmit common data out and Receive from all devices in parallel so that we don't have to poll anymore - meaning we could get all my data back in on transaction and not 8 polls! Data would then be exchanged with the Pi5/CM5 with the normal SPI port @ ~ 40Mhz - also don't need buffers hopefully and maybe get feedback on cable shorts etc.
This also allows us to buffer the data a little (PSRAM) if the Pi5/CM5 is busy - We are looking at custom real time kernels as without this we have to deal with all the data 8K @ 100Hz, with this solution bandwidth use of Pi/CM5 port drops from 90% to less than 10!
Happy to make this HAT an open source design as it helps to solve a lot of problems at once
We have a case very similar to viewtopic.php?t=347749
We want to use the PIO feature to drive an SPI port - with SCLK x 1,MOSI x 1, MISO x 8, CS_MUX x 3
We have a system already (Pi5/CM5) with 8 SPI devices (STM32G474 x8 - each with very high speed ADC x 4 - each running at 2Mhz - busy with processing @ 100Hz for results)
But due to cable lengths of 1.2 meters to each of the devices (star pattern) standard 74HC244 buffering and IDC cables bandwidth is limited to ~ 5MHz - this is with normal polling of each device - I can broadcast to all devices to sync them for aligned results.
We do not want to use LVDS as it stops being as flexible and would need more refinement. The current design is straight logic with a Custom Pi HAT - 4 layers - good layout slew resistors, termination at each end etc - with individual buffering to each cable. Some latency has been seen in the 74HC151 used (tried other HCT/AC etc as well)
We want to Make a smarter HAT with a RP2350B that can Transmit common data out and Receive from all devices in parallel so that we don't have to poll anymore - meaning we could get all my data back in on transaction and not 8 polls! Data would then be exchanged with the Pi5/CM5 with the normal SPI port @ ~ 40Mhz - also don't need buffers hopefully and maybe get feedback on cable shorts etc.
This also allows us to buffer the data a little (PSRAM) if the Pi5/CM5 is busy - We are looking at custom real time kernels as without this we have to deal with all the data 8K @ 100Hz, with this solution bandwidth use of Pi/CM5 port drops from 90% to less than 10!
Happy to make this HAT an open source design as it helps to solve a lot of problems at once
Statistics: Posted by Spam_4_tea — Thu Dec 04, 2025 9:37 am