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Interfacing (DSI, CSI, I2C, etc.) • MIPI CSI2 TX IP and RP1_CFE compability

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Can I mention people here to grab their attention? @raspwan was posting about use of FGPA to stream something into RPi.

I'd like to know how to get matching settings in terms of link speeds? The Xilinx IP has setting called "Line Rate", but `rp1_cfe` driver seem to be multiplying link frequency by 2 for data link speed. I'm trying to understand the relationship here:
  • is the "Line Rate" in the IP setting speed of a single CSI2 lane?
  • is the speed going out from ` sensor_link_rate()` function a speed of a single lane or speed of the bus (all four lanes)?
Any help appreciated.

Statistics: Posted by michal.fita — Thu Mar 07, 2024 2:33 pm



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